A BiCS (Bit Cost Scalable) memory multilayered in the vertical direction and formed by collective processing in order to suppress the increase in process cost has been proposed as a NAND flash memory.
In this BiCS memory, a cylindrical memory hole is formed through a plurality of electrodes stacked on a semiconductor substrate at once, and a memory film is formed on the inner wall of the memory hole. After that, polysilicon serving as a channel is formed inside the memory hole. Consequently, a NAND string (memory string) including a plurality of MONOS memory cells connected in series in the stacking direction can be formed at once. It is also possible to achieve a memory capacity higher than that of the conventional floating gate type NAND flash memory.
In this BiCS memory, the diffusion layers (source/drain) of a selection transistor are formed by implanting impurity ions into the same polysilicon as that of the channel. An erase operation is performed by injecting, into a memory cell, holes generated by a GIDL (Gate-Induced Drain Leakage) current in the junction interface between the diffusion layers and channel of the selection transistor. However, ion implantation into the diffusion layers becomes difficult as the thickness of the channel decreases. This decreases the GIDL current and deteriorates the erase characteristic.
Also, the mobility of electric charge decreases as the thickness of the channel decreases or the number of stacked layers increases. That is, the channel electric current reduces, and the operating speed decreases.
Demands have arisen for solving the problems such as the decrease in channel thickness and the increase in number of stacked layers, which has been posed as the micropatterning and the density growth of the memory increase.